04507847 is referenced by 60 patents and cites 14 patents.

A process for forming high performance npn bipolar transistors in an enhanced CMOS process using only one additional mask level. The bipolar transistor is formed using a low dose blanket implant to form the base in the substrate n-well, then applying arsenic-implanted polysilicon to form the emitter. The emitter formation involves forming a blanket polysilicon layer over the wafer, then using the additional photomask to confine the subsequent arsenic implant to the emitter, n.sup.+ and polysilicon contact regions, prior to application of aluminum metallization. The arsenic implanted polysilicon technique provides state-of-the-art bipolar processing as well as improved contact characteristics. The combined polysilicon-aluminum metallization improves step coverage, circuit reliability, and reduces the possibility of aluminum diffusion (spiking) through junctions. The n-type contact resistance is improved by virtue of being implanted with arsenic; the p-type contact resistance is controlled by the diffusion from the p.sup.+ regions which dope the polysilicon during the emitter drive-in cycle.

Method of making CMOS by twin-tub process integrated with a vertical bipolar transistor
Application Number
Publication Number
Application Date
June 22, 1982
Publication Date
April 2, 1985
Paul A Sullivan
Fort Collins
Casimer K Salys
J T Cavender
NCR Corporation
B01J 17/00
H01L 21/265
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