04495628 is referenced by 55 patents and cites 4 patents.

A CMOS LSI or VLSI integrated circuit chip includes a shift register circuit that provides internal delay testing capability. The shift register circuit is disposed around the periphery of the chip and includes a large number of serially connected stages. One mode of operation allows a data signal to pass through the shift register circuit at a speed limited only by the propagation delays associated with the individual stages thereof. In this mode of operation, one net inversion is introduced into the data path and the output of a final stage of the shift register circuit is coupled to the input of a first stage of the shift register circuit, thereby creating a ring oscillator. The period of oscillation of this ring oscillator represents a measure of the average propagation delay times associated with the various circuit elements employed within the LSI or VLSI circuitry. Such delay measurements can readily be made at any level of packaging or system operation.

Title
CMOS LSI and VLSI chips having internal delay testing capability
Application Number
6/389573
Publication Number
4495628
Application Date
June 17, 1982
Publication Date
January 22, 1985
Inventor
John J Zasio
Sunnyvale
CA, US
Agent
Bryant R Gold
Assignee
Storage Technology Partners
CO, US
IPC
G11C 19/28
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