04495603 is referenced by 32 patents and cites 5 patents.

A semiconductor memory system is organized into a plurality of segments and is equipped with multiplexed or multifunctional pin for input/output purposes; e.g. the memory address pins, since there is a portion of each memory cycle during which the logic state of the address pins is unimportant. Logic means is provided for coupling the multiplexed pins to the memory segments through the input/output lines upon the occurrence of a test clock signal. The test clock signal is generated during the don't-care portion of the memory cycle.

Title
Test system for segmented memory
Application Number
6/174112
Publication Number
4495603
Application Date
July 31, 1980
Publication Date
January 22, 1985
Inventor
Ramesh C Varshney
2622 Ohlone Dr., San Jose, 95132
CA, US
Agent
Harry M Weiss
IPC
G11C 7/00
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