04493033 is referenced by 14 patents and cites 5 patents.

A data processing system handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.

Title
Dual port cache with interleaved read accesses during alternate half-cycles and simultaneous writing
Application Number
143974
Publication Number
4493033
Application Date
December 6, 1982
Publication Date
January 8, 1985
Inventor
Michael B Druke
Chelmsford
MA, US
Michael L Ziegler
Whitinsville
MA, US
Agent
Robert F O Connell
Assignee
Data General Corporation
MA, US
IPC
G06F 13/00
G06F 9/00
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