A video processing system including a number of frame stores with common highways. A number of input ports together with a computer have access to the input highway via buffers and the output ports together with the computer have access to the output highway via buffers. Each port together with the computer is allocated sequential time slots of short duration by a time slot control. Thus to an operator it will seem that he has continuous access to the system. Image planes greater than normal frame size can be handled by the address control. Additional data paths and processing hardware may be provided to enhance the system capabilities.