04462090 is referenced by 108 patents and cites 7 patents.

Disclosed is a semiconductor memory element having a semiconductor substrate of P conductivity type, source and drain regions which are of N conductivity type and formed in the substrate, a first gate insulation layer formed on the major surface of the substrate, corresponding to a channel region located between the source and drain, a floating gate electrode formed on the first gate insulation layer so as to partially overlap the channel region, a second gate insulation layer formed on the floating gate electrode, a control gate electrode formed on the second gate insulation layer so as to partially overlap the floating gate electrode, and an addressing gate electrode formed on the control gate electrode, extending to a portion of the channel region not covered by the floating gate electrode and the control gate electrode.

Title
Method of operating a semiconductor memory circuit
Application Number
103375
Publication Number
4462090
Application Date
June 30, 1982
Publication Date
July 24, 1984
Inventor
Hisakazu Iizuka
Yokohama
JP
Agent
Oblon Fisher Spivak McClelland & Maier
Assignee
Tokyo Shibaura Denki Kabushiki Kaisha
JP
IPC
H01L 29/04
H01L 27/02
H01L 29/78
G11C 11/40
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