04456954 is referenced by 155 patents and cites 7 patents.

Translation look aside buffer (TLB) hardware is provided in a central processor (CP) that receives the results of double-level address translations to eliminate the need for having shadow tables for the second-level in a virtual machine (VM) environment. Hardware is provided for indicating whether a requested address sent by the CP Instruction Execution (IE) unit for translation is a guest or host/native request, and for a guest request whether it is a real or virtual address. Intermediate translations for a double-level translation may or may not be inhibited from being loaded into the TLB. Guest entries may be purged from the TLB without disturbing any host entries. An accelerated preferred guest mode in the CP forces single-level translation hardware to translate each accelerated preferred guest request. A non-accelerated guest request may instead be translated by microcode. A limit check register is provided to check preferred guest addresses without causing performance degradation.

Title
Virtual machine system with guest architecture emulation using hardware TLBs for plural level address translations
Application Number
6/273532
Publication Number
4456954
Application Date
June 15, 1981
Publication Date
June 26, 1984
Inventor
Ethel L Richardson
Poughkeepsie
NY, US
Bruce L McGilvray
Pleasant Valley
NY, US
Peter H Gum
Poughkeepsie
NY, US
Thomas O Curlee III
Poughkeepsie
NY, US
Robert J Bullions III
Poughkeepsie
NY, US
Agent
Bernard M Goldman
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 9/32
G06F 9/44
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