04445174 is referenced by 126 patents and cites 21 patents.

A control system for interlocking processors in a multiprocessing organization. Each processor has its own high speed store in buffer (SIB) cache and each processor shares a common cache with the other processors. The control system insures that all processors access the most up-to-date copy of memory information with a minimal performance impact. The design allows read only copies of the same shared memory block (line) to exist simultaneously in all private caches. Lines that are both shared and changed are stored in the common shared cache, which each processor can directly fetch from and store into. The shared cache system dynamically detects and moves lines, which are both shared and changed, to the common shared cache and moves lines from the shared cache once sharing has ceased.

Title
Multiprocessing system including a shared cache
Application Number
6/249526
Publication Number
4445174
Application Date
March 31, 1981
Publication Date
April 24, 1984
Inventor
Robert P Fletcher
Poughkeepsie
NY, US
Agent
Jack M Arnold
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 13/00
View Original Source