For an error recovery system, one of processors (21) produces an error signal upon occurrence of an error to suspend execution of a particular instruction and to keep retry enable and status signals related to the particular instruction. In the system, a diagnostic unit (30) comprises a storage circuit (76) responsive to the retry enable signal for taking over the status signals directly from the frist processor rather than via a common main memory (20). On occurrence of the error, another of the processors (22) produces a ready signal after completion of execution of an instruction being executed. Responsive to the retry enable and ready signals, the diagnostic unit transfers the status signals to another processor from the storage circuit directly rather than via the main memory to make another processor execute the particular instruction. The error signal may be sent to the diagnostic unit and/or the second processor.