Three level memory hierarchy using write and share flags United States Patent 04442487

04442487 is referenced by 133 patents and cites 12 patents.

A multiprocessing three level memory hierarchy implementation is described which uses a "write" flag and a "share" flag per page of information stored in a level three main memory. These two flag bits are utilized to communicate from main memory at level three to private and shared caches at memory levels one and two how a given page of information is to be used. Essentially, pages which can be both written and shared are moved from main memory to the shared level two cache and then to the shared level one cache, with the processors executing from the shared level one cache. All other pages are moved from main memory to the private level two and level one caches of the requesting processor. Thus, a processor executes either from its private or shared level one cache. This allows several processors to share a level three common main memory without encountering cross interrogation overhead.

Title
Three level memory hierarchy using write and share flags
Application Number
6/336521
Publication Number
4442487
Application Date
December 31, 1981
Publication Date
April 10, 1984
Inventor
Irving Wladawsky Berger
New York
NY, US
David M Stein
Pleasantville
NY, US
Robert P Fletcher
Poughkeepsie
NY, US
Agent
Jack M Arnold
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 13/00
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Citations: 133 (view full list)

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