A single-chip microprocessor device of the MOS/LSI type contains an ALU, several interal busses, a number of address/data registers, and an instruction register with associated control decode or microcontrol generator circuitry. The device communicates with external memory and peripherals by a bidirectional multiplexed address/data bus and a number of control lines. Each instruction word produces a sequence of microcodes which are generated by selecting an entry point for the first address of the control ROM then executing a series of jumps, depending upon the instruction. Usually operands must be fetched from memory and the result stored in memory. Operating speed is increased by fetching the next instruction and starting to generate operand addresses before the current result has been calculated and stored. The microprocessor can perform a memory access operation and an ALU operation in the same machine cycle.