04394731 is referenced by 91 patents and cites 6 patents.

A multiprocessor (MP) system is described having central processors (CPs) in which each CP has a store-in-cache (SIC) with an associated processor directory (PD). Each PD has a plurality of line entries which define the content of corresponding line positions in the associated SIC. Each line entry has an associated data shareability control bit, designated EX, which may be set to a one or zero state to indicate, respectively, the exclusive (EX) or readonly (RO) state of the associated line. An exclusive line is not shareable, but a readonly line is shareable i.e. may exist validly in more than one SIC in the MP. Any CP in the MP can request data in an EX state from its SIC, which data may or may not be found in its SIC or in another CP's SIC. If a CP requests a line of storage data in EX state and the line is found in EX state in another CP's SIC, it may be allowed to remain in the other CP's SIC by being set to RO state in both CPU SICs for the situations in which: (1) the line is found unchanged in EX state in the other CP's SIC, or (2) the line is found in RO state in the other CP's SIC, in which case the line is received and set to RO state in the requesting SIC even though requested in EX state. But if the line is found to be changed in the other CP's SIC, its shareability designation in the requesting SIC will be EX and the line is invalidated in the other CP's SIC from where it is castout.

Cache storage line shareability control for a multiprocessor system
Application Number
Publication Number
Application Date
November 10, 1980
Publication Date
July 19, 1983
Bruce L McGilvray
Pleasant Valley
Richard N Gustafson
Hyde Park
Frederick O Flusche
Hyde Park
Bernard M Goldman
International Business Machines Corporation
G06F 15/16
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