04380046 is referenced by 344 patents and cites 12 patents.

An apparatus for processing multidimensional data with strong spatial characteristics, such as raw image data, characterized by a large number of parallel data streams in an ordered array, comprises a large number (e.g. 16,384 in a 128.times.128 array) of parallel processing elements operating simultaneously and independently on single bit slices of a corresponding array of incoming data streams under control of a single set of instructions. Each of the processing elements comprises a bidirectional data bus in communication with a register for storing single bit slices together with a random access memory unit and associated circuitry, including a binary counter/shift register device, for performing logical and arithmetical computations on the bit slices, and an I/O unit for interfacing the bidirectional data bus with the data stream source. The massively parallel processor architecture enables very high speed processing of large amounts of ordered, parallel data, including spatial translation by shifting or "sliding" of bits vertically or horizontally to neighboring processing elements.

Title
Massively parallel processor computer
Application Number
6/41143
Publication Number
4380046
Application Date
May 21, 1979
Publication Date
April 12, 1983
Inventor
Lai Wo Fung
Morristown
NJ, US
Robert A Administrator of the National Aeronautics and Space Administration with respect to an invention of Frosch
Morristown
NJ, US
Agent
John O Tresansky
John R Manning
Ronald F Sandler
IPC
G06F 15/347
G06F 15/16
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