04376947 is referenced by 66 patents and cites 9 patents.

An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates positioned beneath control gates formed by row address lines. The cells may be electrically programmed by applying selected voltages to the source, drain, control gate and substrate; the floating gate is charged through an insulator between the floating gate and the channel. A simplified process for fabrication of the devices eliminates photoresist and implant steps yet produces improved characteristics in the form of higher gain and lower body effect.

Title
Electrically programmable floating gate semiconductor memory device
Application Number
6/72504
Publication Number
4376947
Application Date
September 4, 1979
Publication Date
March 15, 1983
Inventor
Jih Chang Lien
Sugar Land
TX, US
Te Long Chiu
Houston
TX, US
Agent
John G Graham
Assignee
Texas Instruments Incorporated
TX, US
IPC
G11C 11/40
H01L 29/78
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