04349871 is referenced by 48 patents and cites 6 patents.

A cached multiprocessor system operated in an ordered pipeline timing sequence in which the time slot for use of the cache is made long enough to permit only one cache access. Further, the time slot for data transfers to and from the processors succeeds the time slot for accessing the cache. The sequence is optimized for transactions that require only one cache access, e.g., read operations that hit the cacgenerally require a second cache access in order to update or allocate the cache. These transactions are entered into a queue with order preserved prior to permitting a second access to the cache. Also, a duplicate tag store is associated with the queue and maintained as a copy of the tag store in the cache. Whenever a cache tag is to be changed, a duplicate tag in the duplicate tag store is changed prior to changing the cache tag. The duplicate tag store thus always provides an accurate indication of the contents of the cache. The duplicate tag store is used to determine whether a second access to the cache for an update is necessary.

Title
Duplicate tag store for cached multiprocessor system
Application Number
6/116151
Publication Number
4349871
Application Date
January 28, 1980
Publication Date
September 14, 1982
Inventor
Richard F Lary
Colorado Springs
CO, US
Agent
Cesari and McKenna
Assignee
Digital Equipment Corporation
MA, US
IPC
G06F 13/00
View Original Source