04342102 is referenced by 67 patents and cites 4 patents.

An improved read-only memory arrangement for generating a differential output signal within the memory array itself incorporates a column of reference cell transistors and a single reference bit line within the same general area occupied by the memory cell transistors and memory main bit lines. Each word line is coupled to the gate of one of the reference cell transistors as well as to the gates of the memory cell transistors lying in the same row. The reference bit line voltage is maintained substantially midway between the high and low potential levels of the main bit lines to produce a differential output voltage for sensing purposes.

Title
Semiconductor memory array
Application Number
6/160725
Publication Number
4342102
Application Date
June 18, 1980
Publication Date
July 27, 1982
Inventor
Deepraj S Puar
Sunnyvale
CA, US
Agent
Thomas A Briody
Robert T Mayer
Jerry A Dinardo
Assignee
Signetics Corporation
CA, US
IPC
G11C 7/00
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