04342078 is referenced by 49 patents and cites 13 patents.

A data processor which includes an instruction register for storing a macroinstruction to be executed, a decoder responsive to the stored macroinstruction for generating two or more starting addresses, and a selector which receives the starting addresses generated by the decoder and which selects one of the starting addresses as a next address in response to one or more selection signals. The data processor also includes a control structure which receives the next address chosen by the selector and which selects one of the starting addresses as a next address in response to one or more selection signals. The data processor also icludes a control structure which receives the next address chosen by the selector and which, in response to the next address, derives the selection signals to which the selector will respond in order to select a subsequent next address. The decoder and selector may be adapted such that an additional starting address is provided to the selector such that the selector chooses this additional starting address regardless of the condition of the one or more selection signals generated by the control structure. The control structure may be implemented with a microprogrammed control store containing a plurality of microinstruction routines each having a corresponding starting address such that the starting addresses generated by the decoder correspond to various microinstruction routines contained in the microprogrammed control store.

Title
Instruction register sequence decoder for microprogrammed data processor and method
Application Number
6/41202
Publication Number
4342078
Application Date
May 21, 1979
Publication Date
July 27, 1982
Inventor
Thomas G Gunter
Austin
TX, US
Harry L Tredennick
Austin
TX, US
Agent
Anthony J Sarli Jr
Assignee
Motorola
IL, US
IPC
G06F 9/26
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