A commutator-type data store (102) is serially connected to a variable length shift register (104). Data is first written in the commutator store at the incoming varying line rate. A predetermined time later, the stored bits are read out from the commutator-type store and stored in the shift register at a given rate. Finally, the shift register data is read out at a constant predetermined rate. The length of the shift register is controlled by a counter (110). The phase relationship between the commutator write and read cycles is monitored by logic circuitry (501, 502, 503, 504, 505, 506) within the control unit (106). If this phase relationship has increased by a preselected amount, the commutator readout rate is increased along with the length of the shift register. Alternatively, if the phase relationship has decreased by a preselected amount, the commutator store readout rate is decreased along with a decrease of the shift register length.