04325120 is referenced by 199 patents and cites 9 patents.

A data processor architecture wherein the processors recognize two basic types of objects, an object being a representation of related information maintained in a contiguously-addresed set of memory locations. The first type of object contains ordinary data, such as characters, integers, reals, etc. The second type of object contains a list of access descriptors. Each access descriptor provides information for locating and defining the extent of access to an object associated with that access descriptor. The processors recognize complex objects that are combinations of objects of the basic types. One such complex object (a context) defines an environment for execution of objects accessible to a given instance of a procedural operation. The dispatching of tasks to the processors is accomplished by hardware-controlled queuing mechanisms (dispatching-port objects) which allow multiple sets of processors to serve multiple, but independent sets of tasks. Communication between asynchronous tasks or processes is accomplished by related hardware-controlled queuing mechanisms (buffered-port objects) which allow messages to move between internal processes or input/output processes without the need for interrupts. A mechanism is provided which allows the processors to communicate with each other. This mechanism is used to reawaken an idle processor to alert the processor to the fact that a ready-to-run process at a dispatching port needs execution.

Title
Data processing system
Application Number
5/971661
Publication Number
4325120
Application Date
December 21, 1978
Publication Date
April 13, 1982
Inventor
Roger C Swanson
Portland
OR, US
Justin R Rattner
Aloha
OR, US
George W Cox
Portland
OR, US
Stephen R Colley
Aloha
OR, US
Agent
Owen L Lamb
Assignee
Intel Corporation
CA, US
IPC
G06F 13/00
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