04319356 is referenced by 63 patents and cites 5 patents.

A self-correcting memory system includes internal error detection and correction circuitry that periodically accesses each data word and a group of ECC check bits associated with each data word stored in the memory system. The error detection and correction circuitry includes an ECC checking circuit that receives the accessed data word, generates ECC bits, and compares those ECC bits to the group of ECC check bits associated with the data word. The resulting signal is used to correct any single bit in error, and to indicate the presence of a double bit error. A self-correct address counter is cascaded to a refresh address counter in the control circuitry of the memory system so that the accessing of each data word occurs during a refresh cycle of the memory system.

Title
Self-correcting memory system
Application Number
6/105185
Publication Number
4319356
Application Date
December 19, 1979
Publication Date
March 9, 1982
Inventor
David B Schuck
Escondido
CA, US
James E Kocol
Escondido
CA, US
Agent
Stephen F Jewett
Edward Dugas
J T Cavender
Assignee
NCR Corporation
OH, US
IPC
G06F 11/10
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