04317180 is referenced by 127 patents and cites 3 patents.

An electronic data processing system such as utilized in battery powered hand held calculators having a two mode clock control for control of power consumption. A power consumption controller enables generation of clock signals in an active cycling state for operating the data processing system in an active mode and enables generation of clock signals in a predefined steady state for operating the data processing system in a low power standby mode. In another embodiment of this invention, the power consumption controller generates a preset signal during the standby mode, this preset signal being applied to certain critical circuits of the data processing system to force each critical circuit output to a designer predefined output logic level during the standby mode. The designer predefined output logic level of each critical circuit is selected to prevent static power loads in the standby mode caused by node self discharge.

Title
Clocked logic low power standby mode
Application Number
6/106429
Publication Number
4317180
Application Date
December 26, 1979
Publication Date
February 23, 1982
Inventor
Kenneth A Lies
Lubbock
TX, US
Agent
Melvin Sharp
Leo N Heiting
Robert D Marshall Jr
Assignee
Texas Instruments Incorporated
TX, US
IPC
G06F 1/04
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