04302766 is referenced by 80 patents and cites 2 patents.

A non-volatile semiconductor memory device of the electrically erasable type employs a floating gate which is programmed by application to high voltage across the source and drain so that hot electrons traverse the gate oxide. The floating gate is discharged by electron tunneling through an erase window which is separated from the control gate. Very small cell size is provided by a triple level polysilicon structure.

Title
Self-limiting erasable memory cell with triple level polysilicon
Application Number
6/1097
Publication Number
4302766
Application Date
January 5, 1979
Publication Date
November 24, 1981
Inventor
Te Long Chiu
Houston
TX, US
Daniel C Guterman
Houston
TX, US
Agent
John G Graham
Assignee
Texas Instruments Incorporated
TX, US
IPC
B01J 17/00
H01L 27/02
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