04264953 is referenced by 49 patents and cites 4 patents.

A computer system includes a main memory and a cache memory arrangement, wherein a cache memory unit is associated with each of the several CPU's in the system. Each cache responds to the virtual address signals issued by the associated CPU, in parallel with a mapper unit which, in turn, converts the virtual address signals to physical address signals for addressing the main memory. The cache is subdivided into subunits each responding to a particular program of a multiprogram CPU. When any of the CPUs address a shared portion of the main memory, the mapper unit recognizes the address of the shared portion of the main memory and issues an inhibit signal to inhibit the operation of the cache memory unit to prevent data from the shared portion of the main memory from being stored in the cache.

Title
Virtual cache
Application Number
6/25679
Publication Number
4264953
Application Date
March 30, 1979
Publication Date
April 28, 1981
Inventor
Thomas L Phinney
Phoenix
AZ, US
Robert H Douglas
Phoenix
AZ, US
Agent
Mitchell J Halista
Lockwood D Burton
Assignee
Honeywell
MN, US
IPC
G06F 13/00
G06F 15/16
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