04258378 is referenced by 46 patents and cites 2 patents.

An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates, and electrically erased power voltages applied to the source, drain, control gate and substrate. The floating gate discharges through the insulator between the floating gate and the control gate, i.e., between first and second level polysilicon. An enhancement mode transistor in series with the floating gate device in each cell provides an improved voltage window for deprogramming by allowing the transistor created by the floating gate to go into the depletion mode. The threshold of this series enhancement transistor is lowered by an implant step in the process which is self-aligning.

Title
Electrically alterable floating gate memory with self-aligned low-threshold series enhancement transistor
Application Number
5/909902
Publication Number
4258378
Application Date
May 26, 1978
Publication Date
March 24, 1981
Inventor
Lawrence S Wall
Houston
TX, US
Agent
John G Graham
Assignee
Texas Instruments Incorporated
TX, US
IPC
H01L 27/02
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