04253059 is referenced by 70 patents and cites 3 patents.

On-chip circuitry for measuring the threshold voltage and hence the data retention reliability of the floating gate transistors used in erasable programmable read-only computer memories. Upon the application of a program "verification" signal, an externally adjustable and calibrated voltage ramp is applied by the test circuit to each of the memory X-lines coupled to the gate elements of the memory transistors. The threshold voltage of a selected transistor can then be determined by increasing the voltage ramp to the point at which the transistor will read out.

Title
EPROM Reliability test circuit
Application Number
6/39096
Publication Number
4253059
Application Date
May 14, 1979
Publication Date
February 24, 1981
Inventor
Rajesh H Parekh
San Jose
CA, US
Antony G Bell
Sunnyvale
CA, US
Agent
Michael J Pollock
Theodore Scott Park
Paul J Winters
Assignee
Fairchild Camera & Instrument
CA, US
IPC
G01R 15/12
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