04228496 is referenced by 317 patents and cites 13 patents.

A multiprocessor system the kind in which two or more separate processor modules are interconnected for parallel processing includes two redundant interprocessor buses dedicated exclusively to interprocessor communication. Any processor module may send information to any other processor module by either bus. The buses are shared in use by the processor modules on a time-sharing basis. Use of each bus is controlled by a special bus controller.

The multiprocessor system includes an input/output system having multi-port device controllers and input/output buses connecting each device controller for access by the input/output channels of at least two different processor modules. Each device controller includes logic which insures that only one port is selected for access at a time.

The multiprocessor system includes a distributed power supply system which insures nonstop operation of the remainder of the multiprocessor system in the event of a failure of a power supply for a part of the system. The distributed power supply system includes a separate power supply for each processor module and two separate power supplies for each device controller. Either one of the two power supplies provides the entire power for the device controller in the event the other power supply fails. The distributed power supply system permits any processor module or device controller to be powered down so that on-line maintenance can be performed in a power-off condition while the rest of the multiprocessor system is on-line and functional.

The multiprocessor system includes a memory system in which the memory of each processor module is divided into four logical address areas--user data, system data, user code and system code. The memory system includes a map which translates logical addresses to physical addresses and which coacts with the multiprocessor system to bring pages from secondary memory into primary main memory as required to implement a virtual memory system. The map also provides a protection function. It provides inherent protection among users in a multiprogramming environment, isolates programs from data and protects system programs from the actions of user programs. The map also provides a reference history information for each logical page as an aid to efficient memory management by the operating system.

The multiprocessor system includes in the memory of each processor module an error detection and correction system which detects all single bit and double bit errors and which corrects all single bit errors in semiconductor memory storage.

Title
Multiprocessor system
Application Number
5/721043
Publication Number
4228496
Application Date
September 7, 1976
Publication Date
October 14, 1980
Inventor
Steven W Wierenga
Sunnyvale
CA, US
James G Treybig
Sunnyvale
CA, US
Dennis L McEvoy
Scotts Valley
CA, US
David R Mackie
Ben Lomond
CA, US
Steven J Hayashi
Cupertino
CA, US
David A Greig
Cupertino
CA, US
Michael D Green
Los Altos
CA, US
Peter J Graziano
Los Altos
CA, US
John A Despotakis
Pleasanton
CA, US
William H Davidow
Atherton
CA, US
Richard M Bixler
Sunnyvale
CA, US
Joel F Bartlett
Palo Alto
CA, US
James A Katzman
San Jose
CA, US
Agent
Donald C Feix
Assignee
Tandem Computers Incorporated
CA, US
IPC
G06F 15/06
G06F 15/16
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