A first phase locked loop produces a local oscillator signal. The output of a second phase locked loop is connected to the input of the first phase locked loop. A first variable frequency divider is connected in the first phase locked loop. A second variable frequency divider having the same frequency division ratio as the first frequency divider is connected between a variable frequency oscillator and the input of the second phase locked loop. An adder adds a base frequency of preferably 1 MHz to the output frequency of the second frequency divider. With the frequency of the variable frequency oscillator set at a center frequency, the frequency of the local oscillator signal is equal to the frequency division ratio of the frequency dividers multiplied by 1 MHz. Any variation in the frequency of the variable frequency oscillator from the center frequency is algebraically added to the local oscillator frequency, regardless of the frequency division ratio, as an offset frequency. The frequency range of the variable frequency oscillator is low compared to the frequency range of the local oscillator signal, thereby enabling low frequency drift. A gate disables the first phase locked loop when the second phase locked loop is not in lock.