04205373 is referenced by 74 patents and cites 4 patents.

A method and system for accessing a memory subsystem from a requesting subsystem connected to a first bus. The memory subsystem is connected to a second bus. A pair of adaptors coupled to each other by a cable are respectively connected to the first and second busses. The requesting subsystem has a plurality of input/output paths from which a memory message can be transmitted to the first bus. Each such transmitted memory message includes a source code identifying the address of the requesting subsystem on the first bus and a tag bit identifying the one of the input/output paths from which the memory message is transmitted. The first adaptor has the same address on the first bus as the memory subsystem has on the second bus and receives a memory message addressed to the memory subsystem. A second adaptor determines whether a response message from the memory is required by the memory message and, if so, stores the first source code and tag bit and inserts a second source code identifying the address of the second adaptor on the second bus and a second tag bit identifying the location of the stored source code and tag bit. The second adaptor then transmits the modified memory message to the memory subsystem. If a response message is required, the memory subsystem transmits the response message back to the second adaptor, which re-inserts the stored source code and tag bit and transmits the modified memory response message back to the requesting subsystem, which routes the modified response message to the input/output path determined by the first tag bit.

System and method for accessing memory connected to different bus and requesting subsystem
Application Number
Publication Number
Application Date
May 22, 1978
Publication Date
May 27, 1980
James F Taylor
Niranjan S Shah
Stephen F Jewett
Edward Dugas
J T Cavender
NCR Corporation
G06F 3/04
G06F 13/00
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