04169284 is referenced by 30 patents and cites 6 patents.

The disclosure enables concurrent access to a cache by main storage and a processor by means of a cache control which provides two cache access timing cycles during each processor storage request cycle. The cache is accessible to the processor during one of the cache timing cycles and is accessible to main storage during the other cache timing cycle. No alternately accessible modules, buffering, delay, or interruption is provided for main storage line transfers to the cache.

Title
Cache control for concurrent access
Application Number
5/884301
Publication Number
4169284
Application Date
March 7, 1978
Publication Date
September 25, 1979
Inventor
Edward C Wong
Poughkeepsie
NY, US
Carleton E Werve
Poughkeepsie
NY, US
Spurgeon G Hogan
Poughkeepsie
NY, US
Agent
Bernard M Goldman
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 13/00
View Original Source