04168523 is referenced by 36 patents and cites 4 patents.

A data processor utilizes a central processor controller to determine selectively the next required operation phase while executing a current operation phase. Control words contained in a second stage control memory are selectively addressed from addresses contained in a first stage control memory. The selection of a particular address of a control word contained in said first stage control memory is determined from combinations of signals received by a condition multiplexer interposed between said first and second stage control memories, portions of program instructions contained in main memory, externally operated manual switches, and various internal control flags. The operation phase is defined as an operation, which is defined by said control word. The generation of the address for the next required control word and the execution of the operation defined by the current control word occurs in the same machine cycle. Each control word comprises a mode of operation, control signals for the various execute units, and input signals for the condition multiplexer for determining the next operation phase control word address, required by the data processor in the process of executing program instructions contained in the data processor's main memory.

Title
Data processor utilizing a two level microaddressing controller
Application Number
629740
Publication Number
4168523
Application Date
December 6, 1977
Publication Date
September 18, 1979
Inventor
Ronald L Engelbrecht
Augusta
KS, US
Venu Chari
San Diego
CA, US
Agent
Stephen F Jewett
Edward Dugas
J T Cavender
Assignee
NCR Corporation
OH, US
IPC
G06F 9/20
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