This relates to a signal processor which accepts the linear sum of several continuous (CW) direct sequence, spread spectrum signals, and outputs a sequence of narrow pulses, each of which contains all the available energy of one of the input signals. The CW signals are applied to the input of a tapped delay line, the contents of which are compared, in a parallel fashion, with the output of a code storage register. When correlation has been achieved, a narrow pulse is produced which contains all the available energy of one of the input signals. The circuit reduces the problem of continuously processing several simultaneous signals, conventionally performed with dedicated circuitry for each signal, to a sequential pulse processing operation, effectively timesharing the same single set of circuitry. Both amplitude and phase information is preserved through the processing technique allowing implementation in coherent and non-coherent system architectures.