04141067 is referenced by 59 patents and cites 3 patents.

A multiprocessor system is described in which a plurality of central processor units share the same main memory over a common asynchronous bus. Each central processor directs all memory requests to its own high speed cache memory. If the request is to read data from memory, the cache memory control determines if the addressed data is present in the cache memory. If so, the data is transferred to the processor without accessing main memory over the bus. If the data is not present in the cache memory, the cache memory control gains access to the bus by a priority circuit and reads out the data from memory, storing the data in the cache memory at the same time that it transfers the data to the processor. If the memory request by the processor is to write data in memory, the cache memory control gains access to the bus and initiates a data store in the main memory. At the same time, the cache memory control determines if the existing data being overwritten at the addressed location in main memory is present in the cache memory. If so, it updates the data in the cache memory at the same time it writes the data in main memory.

Title
Multiprocessor system with cache memory
Application Number
5/805834
Publication Number
4141067
Application Date
June 13, 1977
Publication Date
February 20, 1979
Inventor
Angus McLagan
Newport Beach
CA, US
Agent
Christie Parker & Hale
Assignee
General Automation
CA, US
IPC
G06F 13/00
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