A multipurpose speed controllable processor composed of control memories for storing microprograms, register groups for storing instructions as well as data and the internal states of the processor, all of which serve as parts of the micro instructions, and arithmetic logic units which execute the micro instructions from the microprogram. The arithmetic logic units operate in accordance with operand addresses and codes designated in the micro instructions. Switches are provided for transferring the operand addresses of the micro instructions from the control memories to the register groups, for transferring the operands from the register groups to the arithmetic logic units, for transferring to the register groups the results of the operation of the arithmetic logic units, for transferring the operation codes from the control memories to the arithmetic units and for transferring to a control unit special status information of the operation results in the arithmetic logic units. Also provided is a control unit in which the microprograms execution speed is made controllable by writing control information in an execution speed setting register in the controller. Such control information serves to divide the control memories into valid and invalid parts. Also, the valid control memories are divided into an arbitrary number of control memory groups, each group being subdivided into an arbitrary number of control memory subgroups. The number of arithmetic logic units to be assigned to each control memory group is also controlled. Additionally, information designating the execution modes of the micro instructions stored in each control memory group is also included in the control information. The control unit controls the other parts so that micro instructions are simultaneously read out from one of the control memory subgroups of all the control memory groups. The read out micro instructions are simultaneously executed in the arithmetic logic units allocated to the control memory groups, and are equal in number to the arithmetic logic units allocated to the control memory groups. Upon execution of all the read out micro instructions, micro instructions of the next cycle and read out immediately or after a certain condition is fulfilled, depending upon the execution mode set in the control memory groups.