04130900 is referenced by 84 patents and cites 1 patents.

A latch circuit is provided on the input side of write-in circuit of a semiconductor memory device which is so formed that a common data line is used for data writing-in and data reading-out. Write-in data read serially into the latch circuit in a word unit is temporarily stored and held, so that the data is written simultaneously into various memory cells for in column units of the memory array.

Title
Memory with common read/write data line and write-in latch circuit
Application Number
5/790815
Publication Number
4130900
Application Date
April 25, 1977
Publication Date
December 19, 1978
Inventor
Masafumi Watanabe
Kawasaki
JP
Agent
Oblon Fisher Spivak McClelland & Maier
Assignee
Tokyo Shibaura Electric
JP
IPC
G11C 7/06
G11C 8/00
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