04122544 is referenced by 42 patents and cites 2 patents.

An N-channel, double level poly, MOS read only memory or ROM array is electrically programmable by floating gates which are interposed between the gate oxide and control gates formed by two address lines. The cells may be electrically erased by applying selected voltages to the source, drain, control gate and substrate; the floating gate discharges through the insulator between the floating gate and the control gate, i.e., between first and second level polysilicon. An enhancement mode transistor in series with the floating gate device in each cell provides an improved voltage window for deprogramming.

Title
Electrically alterable floating gate semiconductor memory device with series enhancement transistor
Application Number
5/754207
Publication Number
4122544
Application Date
December 27, 1976
Publication Date
October 24, 1978
Inventor
David J McElroy
Houston
TX, US
Agent
James T Comfort
John G Graham
Assignee
Texas Instruments Incorporated
TX, US
IPC
G11C 11/40
View Original Source