04112502 is referenced by 155 patents.

A method of and an apparatus for conditionally bypassing the error correction function of a large scale integrated (LSI) semiconductor random access memory (RAM) is disclosed. A content addressable memory (CAM) is utilized to store the addresses of the addressable locations in the RAM in which an error was previously detected, and on each memory reference both the CAM and the RAM are simultaneously referenced by the same address. Upon a memory reference, the read data from, i.e., the date read out of, the RAM is concurrently coupled directly to an Interface Register and directly to the error detection and correction circuitry (ECC) and thence to the Interface Register. If the CAM does not contain the address, the read data that is coupled to the Interface Register is gated out at a first relatively early gate pulse. However, if the CAM does contain the address, the corrected read data from the ECC is then gated out of the Interface Register at a second relatively later gate pulse. Thus, when no error exists in the read data, the RAM is accessed at a relatively fast access time while, if an error exists in the read data, the RAM is accessed at a relatively slower access time to provide the added time required by the ECC to correct the read data.

Title
Conditional bypass of error correction for dual memory access time selection
Application Number
733687
Publication Number
4112502
Application Date
July 18, 1977
Publication Date
September 5, 1978
Inventor
James Herman Scheuneman
St. Paul
MN, US
Agent
Marshall M Truex
William E Cleaver
Kenneth T Grace
Assignee
Sperry Rand Corporation
NY, US
IPC
G06F 1/04
G06F 11/00
G06F 13/00
G06F 11/10
View Original Source