An input/output system couples to a host processor through a system interface unit and includes at least two input/output processing units and a memory unit. The system interface unit includes interrupt processing logic circuits for each input/output processing unit for processing interrupt requests on a priority basis. The system interface unit further includes a processor intercommunication network which connects to each of the interrupt processing logic circuits.
The input/output operating system initiates an input/output operation in response to a connect interrupt generated by the host processor executing a connect instruction. The interrupt is directed to an assigned input/output processing unit by the System Interface Unit (SIU). The assigned processor executes an instruction sequence which causes an appropriate entry to be placed in an operating system queue located within the memory unit. The queue entry has sufficient data to specify the desired I/O operation. The processing unit in control stores information in the memory unit to specify the interrupt priority level of the connect operation, sets an interrupt request at that same priority level, and causes an interrupt at a very high priority level for the other processing unit via the intercommunication network. The high priority level interrupt causes the other processing unit to execute instructions which load the priority level information from the memory unit and set an interrupt request at the specified level. With both processing units having outstanding interrupt request at the specified priority level, the processing unit which completes all of the processes at priority levels higher or equal to that of the queue entry responds to the interrupt first. By having the least busy processing unit respond to the interrupt utilizing the queue entry to initiate the desired input/output operation process, a balance in the utilization of the input/output processing units is insured.