04075704 is referenced by 104 patents and cites 6 patents.

A digital data processor includes a plurality of memory registers, a floating point adder and a floating point multiplier intercoupled by a plurality of simultaneously operable parallel buses facilitating multiple parallel operations during one clock cycle or instruction. The floating adder and multiplier each include a number of stages separated by intermediate temporary storage registers which receive the partial results of a computation for use by the next stage during the next clock period. Floating point additions, multiplications and other arithmetic and logical results are produced during each clock cycle.

Title
Floating point data processor for high speech operation
Application Number
5/702148
Publication Number
4075704
Application Date
July 2, 1976
Publication Date
February 21, 1978
Inventor
George P O Leary
Beaverton
OR, US
Agent
Klarquist Sparkman Campbell Leigh Hall & Whinston
Assignee
Floating Point Systems
OR, US
IPC
G06F 7/38
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