04075686 is referenced by 87 patents and cites 8 patents.

A local memory of an input/output system includes a cache store and a backing store. The system includes a plurality of command modules. The cache store provides fast access to blocks of information previously fetched from the backing store in response to memory commands generated by any one of a plurality of command modules during both data transfer and data processing operations. Each memory command applied to the memory unit incudes a predetermined bit which is coded to designate when the information requested from the local memory unit is to be written into the cache store. The local memory unit includes aparatus operative in response to each memory command to enable the command module to bypass selectively the cache store in accordance with the coding of the predetermined bit thereby enabling the command modules to execute operations more expeditiously during the performance of input/output data transfer operations.

Title
Input/output cache system including bypass capability
Application Number
5/755871
Publication Number
4075686
Application Date
December 30, 1976
Publication Date
February 21, 1978
Inventor
Lawrence W Chelberg
Phoenix
AZ, US
Jaime Calle
Glendale
AZ, US
Agent
Ronald T Reiling
Nicholas Prasinos
Faith F Driscoll
Assignee
Honeywell Information Systems
MA, US
IPC
G06F 13/00
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