04068304 is referenced by 32 patents and cites 7 patents.

A machine for emulating the results of multi-level storage hierarchies by providing an associative storage directory for each level other than main storage. Address sequences to drive the directories are derived from a single level digital computer by recording sequences on tape or by dynamically monitoring computer operation. Individual addresses are skewed an appropriate number of bits depending upon the block size and the number of classes being emulated at any given level, so that those bits of the monitored address indicating segment name are presented to the directory for comparison with its contents in the appropriate class. Means are provided for transposing the segment and class names at higher levels to segment and class names at lower levels. Counting means are provided to record hits, misses and pushes at various levels in order to provide data for calculating average access times for the particular multi-level storage hierarchy being emulated.

Title
Storage hierarchy performance monitor
Application Number
5/320222
Publication Number
4068304
Application Date
January 2, 1973
Publication Date
January 10, 1978
Inventor
Klim Maling
Wappingers Falls
NY, US
William F Beausoleil
Hopewell Junction
NY, US
Agent
Bernard M Goldman
Assignee
International Business Machines Corporation
NY, US
IPC
G06F 1/00
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