04065809 is referenced by 35 patents and cites 8 patents.

A microcomputer system comprising two microcomputers, a read only memory (hereinafter abbreviated as "ROM") and a random access memory (hereinafter abbreviated as "RAM") exclusively used with each of the two microcomputers and a common RAM accessible from the two microcomputers, wherein the microcomputers and memories are connected together; there are provided between the microcomputers and common RAM an address decoder for detecting the access of the respective microcomputers to the common RAM and a control flip-flop circuit which is set when one of the two microcomputers completes a memory access cycle and is reset when the other finishes a memory access cycle; when the transfer of data is not carried out between the two microcomputers, then these microcomputers generally make an access to the corresponding exclusive memories; only when an access to the common RAM is made by the two microcomputers substantially at the same time, then the flip-flop circuit places one of the two microcomputers in a waiting position for memory access until the other finishes a memory access cycle; and in any other case, the two microcomputers carry out arithmetic operation independently of each other.

Title
Multi-processing system for controlling microcomputers and memories
Application Number
5/690603
Publication Number
4065809
Application Date
May 27, 1976
Publication Date
December 27, 1977
Inventor
Mitsuo Matsumoto
Kokubunji
JA
Agent
Oblon Fisher Spivak McClelland & Maier
Assignee
Tokyo Shibaura Electric
JA
IPC
G06F 13/00
G06F 15/16
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