04056844 is referenced by 73 patents and cites 4 patents.

In a data processing system in which a single main memory is shared by two or more basic processing units, each unit is provided with a first buffer address array which stores the addresses of data stored in the associated buffer memory and is searched by this processing unit and with second buffer address arrays which store the copy of the content of the first buffer address array and are searched by the store addresses from the other processing units, so that the information stored in the buffer memory of one processing unit may be prevented from becoming different from the information stored in the main memory when another processing unit performs a storing operation, without degrading the processing efficiency of the system.

Title
Memory control system using plural buffer address arrays
Application Number
5/620757
Publication Number
4056844
Application Date
October 8, 1975
Publication Date
November 1, 1977
Inventor
Chikahiko Izumi
Hatano
JA
Agent
Craig & Antonelli
Assignee
Hitachi
JA
IPC
G06F 13/00
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