04050965 is referenced by 37 patents and cites 9 patents.

A process for the simultaneous fabrication of CMOS transistors and bipolar devices on the same integrated circuit. The process follows the standard Silicon-Gate Deep Depletion technology up through gate definition. An additional mask step is included for definition of the base implant region. After the base diffusion the process again follows the standard approach resulting in a new structure which permits the fabrication of CMOS/SOS as well as a bipolar driver transistor.

Title
Simultaneous fabrication of CMOS transistors and bipolar devices
Application Number
5/624515
Publication Number
4050965
Application Date
October 21, 1975
Publication Date
September 27, 1977
Inventor
John C Sarace
Mission Viejo
CA, US
Alfred C Ipri
Princeton
NJ, US
Agent
George Fine
Joseph E Rusz
Assignee
The United States of America represented by the Secretary of the Air Force
DC, US
IPC
H01L 21/265
H01L 21/84
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