04038646 is referenced by 18 patents and cites 3 patents.

An improved dynamic MOS RAM employing capacitive storage memory cells having a single active device per cell. The RAM includes several improved circuits and techniques which reduce power consumption and pattern sensitivity and which also provide a higher speed memory. Complementary input/output lines are employed which are coupled to alternate pair of the bit-sense lines making the use of a bistable output latch and push-pull output buffer more advantageous. The sense amplifiers associated with each of the bit lines are activated by a dual sloped signal to reduce noise and increase sensitivity and gain in the amplifiers. The output lines of the address buffers are initially "high" and then brought to their final level after an address is received by the buffers.

Title
Dynamic MOS RAM
Application Number
5/666338
Publication Number
4038646
Application Date
March 12, 1976
Publication Date
July 26, 1977
Inventor
Stephen F Dreyer
San Jose
CA, US
Rustam Mehta
Sunnyvale
CA, US
Agent
Blakely Sokoloff Taylor & Zafman
Assignee
Intel Corporation
CA, US
IPC
G11C 11/04
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