A microelectronic package includes a lower unit having a lower unit substrate with conductive features and a top and bottom surface. The lower unit includes one or more lower unit chips overly/ing the top surface of the lower unit substrate that are electrically connected to the conductive features of the lower unit substrate. The microelectronic package also includes an upper unit including an upper unit substrate having conductive features, top and bottom surfaces and a hole extending between such top and bottom surfaces. The upper unit further includes one or more upper unit chips overlying the top surface of the upper unit substrate and electrically connected to the conductive features of the upper unit substrate by connections extending within the hole. The upper unit may include an upper unit encapsulant that covers the connections of the upper unit and the one or more upper unit chips.

Title
Microelectronic package
Application Number
11/894036
Publication Number
20090045524
Application Date
August 16, 2007
Publication Date
February 19, 2009
Inventor
Christopher Wade
Los Gatos
CA, US
Ellis Chau
San Jose
CA, US
Wei Shun Wang
Mountain View
CA, US
Sean Moran
Berlingame
CA, US
Belgacem Haba
Saratoga
CA, US
IIyas Mohammed
Santa Clara
CA, US
Agent
LERNER DAVID et al
NJ, US
Agent
Tessera
NJ, US
Assignee
Tessera
CA, US
IPC
H01L 23/48
H01L 21/50
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