Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

Title
Methods and structures for protecting one area while processing another area on a chip
Application Number
12/106586
Publication Number
20080261128
Application Date
April 21, 2008
Publication Date
October 23, 2008
Inventor
Harald Okorn Schmidt
Arpan P Mahorowala
Bronxville
NY, US
Katherina Babich
Chappaqua
NY, US
Thimothy Dalton
Ridgefield
CT, US
Dirk Pfeiffer
Dobbs Ferry
NY, US
Carl J Radens
LaGrangeville
NY, US
Ramachandra Divakaruni
Ossining
NY, US
Kangguo Cheng
Beacon
NY, US
Kenneth T Settlemyer
Poughquag
NY, US
Deok kee Kim
Wappingers Falls
NY, US
Agent
Whitham Curtis & Christofferson PC
VA, US
IPC
G03F 07/20
G03F 07/04
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