A “smart verify” technique, whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations, is presented. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations by providing “intelligent” means to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. At the beginning of a program/verify cycle sequence only the lowest state or states are checked during the verify phase. As lower states are reached, additional higher states are added to the verify sequence and lower states can be removed.

Title
Smart Verify For Multi-State Memories
Application Number
11/759872
Publication Number
20070234144
Application Date
June 7, 2007
Publication Date
October 4, 2007
Inventor
Yupin Kawing Fong
Fremont
CA, US
Daniel C Guterman
Fremont
CA, US
Geoffrey S Gongwer
Los Altos
CA, US
Agent
Davis Wright Tremaine Sandisk Corporation
CA, US
IPC
G11C 29/00
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