A processor chip is provided. The processor chip includes a plurality of processing cores, where each of the processing cores are multi-threaded. The plurality of processing cores are located in a center region of the processor chip. A plurality of cache bank memories are included. A crossbar enabling communication between the plurality of processing cores and the plurality of cache bank memories is provided. The crossbar includes an arbiter configured to arbitrate multiple requests received from the plurality of processing cores with available outputs. The arbiter includes a barrel shifter configured to rotate the multiple requests for dynamic prioritization, and priority encoders associated with each of the available outputs. Each of the priority encoders have logic gates configured to disable priority encoder outputs. A method for arbitrating requests within a multi-core multi-thread processor is included.

Title
Cache crossbar arbitration
Application Number
10/855060
Publication Number
20050060457
Application Date
May 26, 2004
Publication Date
March 17, 2005
Inventor
Kunle A Olukotun
Stanford
CA, US
Agent
Martine Penilla & Gencarella
CA, US
Assignee
Sun Microsystems
CA, US
IPC
G06F 13/38
G06F 13/14
G06F 12/00
G06F 13/362
G06F 13/36
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