A processor is provided. The processor includes at least two cores. The at least two cores have a first level cache memory and are multi-threaded. A crossbar is included. A plurality of cache bank memories in communication with the at least two cores through the crossbar is provided. Each of the plurality of cache bank memories communicates with a main memory interface. A plurality of input/output interface modules in communication with the main memory interface and providing a link to the at least two cores are included. The link bypasses the plurality of cache bank memories and the crossbar. Threading hardware configured to enable the at least two cores to switch from a first thread to a second thread in a manner hiding delays caused by cache accesses is included. A server and a method for determining when to switch threads in a multi-core multi-thread environment are included.

Title
Multi-core multi-thread processor
Application Number
10/855233
Publication Number
20050044319
Application Date
May 26, 2004
Publication Date
February 24, 2005
Inventor
Kunle A Olukotun
Stanford
CA, US
Agent
Martine & Penilla & Gencarella
CA, US
Assignee
Sun Microsystems
CA, US
IPC
G06F 12/00
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