A novel mask layer is used in the dual damascene construction of an interconnect structure of an integrated circuit device. The interconnect structure has a low-k dielectric material. The mask layer has a passivation film deposited on the low-k dielectric material, a barrier film is deposited over the passivation film and a metallic film is deposited over the barrier film. The metallic film increases the overall etch selectivity of the mask layer to assure a faithful transfer of via and trench features to the low-k dielectric material during the etching steps of the dual damascene process.

Title
Mask layer and interconnect structure for dual damascene semiconductor manufacturing
Application Number
10/699975
Publication Number
20040171256
Application Date
November 2, 2003
Publication Date
September 2, 2004
Inventor
Joseph Ashley Taylor
Orlando
FL, US
Scott Jessen
Orlando
FL, US
Isaiah O Oladeji
Gotha
FL, US
Agent
Beusse Brownlee Wolter Mora & Maire P A
FL, US
IPC
H01L 21/302
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